Ideas Test

3 VOTE

Stream Logic data to external application

I would like an SDK option where my application could command your LogicPro 8 or 16 to gather data from your 12 bit A/D at a specific data rate, with no gaps. It could also "stream" the digital channels the same way.

For example, I would like to gather data at 1 us intervals from your a/d and stream them into my application, with no "restart" gaps.

It is expected that there will be circumstantial upper limits to this data gathering streaming feature, as CPU's, USB ports, hardware, Operating systems, etc., all vary in abilities.

That opens up a world of possibilities for uses and user generated code to your SDK. I can see user developed oscilloscopes, real time sensor monitoring, real time Logic Watching (at reduced sample rates) for other-wise un-catchable logic pattern events of arbitrary complexity.

This mode would be a simple data streaming mode, with no bells and whistles. The user would do the heavy lifting.

  • Avatar32.5fb70cce7410889e661286fd7f1897de Guest
  • Jun 26 2018
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  • Avatar40.8f183f721a2c86cd98fddbbe6dc46ec9
    Guest commented
    June 26, 2018 18:27

    same here!

    my use-case is to decode let's say a uart-protocol and have a standard terminal window running on the side that can sniff, decode and print the data in a standard syslog style format.

    suggest to use either http://libdill.org or nanomsg as a transparent & ultra-fast glue between the saleae process and custom processes wanting to peek at the data.

  • Avatar40.8f183f721a2c86cd98fddbbe6dc46ec9
    Guest commented
    June 26, 2018 18:27

    We're working on a new back end data processing system that will replace how we do data processing now. This new system is very API first, and should be able to do what you want once it's finished. Unfortunately it's still pretty early stages - feel free to check back for updates.
    About the sample rate - the hardware isn't that flexible on rate. The ADC sample rate is fixed, and the FPGA on the device performs integer ratio downsampling, with only power of 2 ratios possible. (eg 1:2, 1:4, 1:8, 1:16, etc). Arbitrary sample rates aren't possible. We may change this to support any integer downsample ratio in the future (i.e. not restricted to powers of 2) which would provide a lot more flexibility, but we would have to remove the digital downsampling filter from the FPGA, leaving higher frequency components aliased in to lower sample rate captures.