Ideas Test


Add a 25 MS/s sample rate for analog channels

When the high sample rates were added for the Pro 8 and Pro 16 (thanks - it's awesome!), an intermediate sample rate for digital channels was introduced at 250 MS/s. This sits between the 500 MS/s and 125 MS/s rates. However, a corresponding intermediate sample rate of 25 MS/s between 50 MS/s and 12.5 MS/s was not introduced for the analog channels even though the post ( states that the bandwidth increase applies to both analog and digital channels. The lack of this intermediate sample rate reduces the flexibility of the analog capture.

A quick check of the Logic 1.2.18 software when configuring a Logic Pro 16 shows that (with no digital channels enabled) that the sample rate drops from 50 MS/s to 12.5 MS/s when going from 5 analog channels enabled to 6 analog channels enabled. This 12.5 MS/s rate is then available for up to all 16 analog channels enabled. This suggests that the Pro 16 could support the proposed intermediate sample rate of 25 MS/s on something like 9-11 channels. I'm sure there are considerations with the hardware/software which I'm not aware of, but presumably the proposed 25 MS/s intermediate sample rate would be feasible.

Could this 25 MS/s intermediate sample rate be added to fill in the gap between 50 MS/s and 12.5 MS/s for analog channels and bring them closer to the configuration flexibility of the digital channels?

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  • Aug 2 2018
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  • Avatar40.8f183f721a2c86cd98fddbbe6dc46ec9
    Guest commented
    August 02, 2018 16:51

    Thanks for the detailed insight, Mark! Got to love the engineering tradeoffs. I'll also throw out that I don't have some burning need for 25 MS/s sampling - just seemed odd that it wasn't available when the "equivalent" rate for digital signals was added. This is very much a low-priority wishlist item (at least for me)!

    I think I recall from somewhere else you (or someone else) mentioned that the FPGA design is somewhere around (or above) 99% utilization. It's honestly impressive that everything works and is crammed in there! I can imagine that Place and Route takes ages. It's also entirely understandable that the solution has to exist on the device itself to keep the USB data rates up.

    Sounds like the answer is "potentially feasible, but our options are limited":
    1. Hardware AA filtering before the ADC is fixed, so no changes available there
    2. The digital AA filter topology doesn't support 2:1 downsampling (ie. 25 MS/s)
    3. Changing the digital AA filter isn't feasible due to space constraints in the FPGA design
    4. Removing the digital AA filter gets configurable downsampling, but introduces aliased signals into the downsampled data
    5. Supporting both approaches is also not feasible due to the FPGA design space constraints which would necessitate software changes (ie. re-flashing the FPGA when the other approach is requested + the code to know when this is necessary)

    Maybe if someone has an epiphany which frees up some FPGA design space, then a different filter topology could support the different sampling rates. Or, if removing the digital AA filter becomes the preferred path forward later on then this could be revisited. Otherwise, keep up the great work and thanks for the response!