Ideas Test


Make a Signal Generator with a Similar Architecture (USB Driven)

You're half done. I love your architecture (use the PC's memory and computational power coupled via a USB to a relatively small device). Now just add a signal generator.

For the first product, a separate signal generator would be fine. But eventually make a "Combi" with a logic analyzer and signal generator in one package (and one USB connection).


  • Avatar32.5fb70cce7410889e661286fd7f1897de Guest
  • Jun 26 2018
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  • Avatar40.8f183f721a2c86cd98fddbbe6dc46ec9
    Guest commented
    June 26, 2018 18:44

    We've spent quite a bit of time thinking about how to do some of the things you've listed @cbarest. Ultimately it comes down to the hardware requirements, as long as those are set up properly the rest of the problem can be solved in hardware.
    The main features I think we want to address are:
    1. input mode (our current products all do this)
    2. output mode
    3. ability to switch a pin from input mode to output mode very quickly
    4. ability to have some pins in the input direction while other pins are in the output direction.
    5. possibly open drain or other drive modes.
    With that, the device should be able to operate as a basic pattern generator, which is the digital equivalent of a signal generator, but also as a bus adapter, effectively allowing it to act as a a master or slave on a number of different protocols.
    One of the big questions is latency. If the device is operating in a closed loop way, performing the processing to decide the next output on the PC will add considerable latency due to the round trip time over USB. That could be reduced, but it still won't be as fast as running closed loop code on the hardware.

  • Avatar40.8f183f721a2c86cd98fddbbe6dc46ec9
    Guest commented
    June 26, 2018 18:44

    With something like this, if we had the ability to output a pattern to each, or multiple lines... perhaps we could create some software that mimics the "JTAGulator" by sequentially reading what's at each test point, then injecting each suspected target point with a pre-defined logic pattern at various rates until the Saleae Logic detects the appropriate read back for that test point.
    Further, if we had the ability to take this new device out of "generator mode" and send signals from the host computer out through this Signal Generator, we could then use our custom software to create our own JTAG auto-detecting in-circuit programmer \ debugger! Right?
    ... Or ...
    Am I so lost I don't even know what I'm talking about?

  • Avatar40.8f183f721a2c86cd98fddbbe6dc46ec9
    Guest commented
    June 26, 2018 18:44

    I would add a logic pattern generator which can take the logic analyzer data captures and play them back.