Ideas Test

1 VOTE

Simple Parallel - Flexible "data valid on" setting instead of only raising/falling edge

The Simple Parallel analyser (which happens to be most used at least around me) has only two options for timing the sample taking: "Data valid on rising clock edge" and "Data valid on falling clock edge". Unfortunately I encountered many situations where this is not enough or leads to errors. An example that is already suggested is that /both/ edges can be important. What happens often here is "Data valid xxx nanoseconds /after/ the (usually) rising edge". There is no chance to set this and we get erroneous results. So the suggestion is to make it flexible with at least three, ideally four options: - rising edge, <time> after rising edge, falling edge, <time> after falling edge.

  • Avatar32.5fb70cce7410889e661286fd7f1897de Guest
  • Jun 26 2018
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  • Avatar40.8f183f721a2c86cd98fddbbe6dc46ec9
    Guest commented
    June 26, 2018 18:37

    I would like to add this, DDR support, and clockless support in the future. I should mention that someone has already used the analyzer SDK to create a custom parallel analyzer that is clockless: https://github.com/Zweikeks/saleae-logic-SimpleParallelNoClock-Analyzer, and we publish the source to our own parallel analyer, if anyone would like to add this feature themselves.